The present invention relates to the fabrication of semiconductor devices and more specifically, to a process for fabricating a vertical conductive region in a semiconductor device using plural epitaxial layers.
As is known, high speed bipolar transistors should have low collector resistance. To this end, a low resistivity region ("buried layer") with the same conductivity type as the collector is placed under the collector. Typically, integrated circuits include a collector contact that is on top of the transistor. To further reduce collector resistance, the collector contact on top of the transistor may be linked to the buried layer with a further low resistivity region denoted a collector sinker.
NPN transistors are used in many integrated circuits because they have better electrical performance than PNP transistors, and because they are easier to fabricate. A common procedure for fabricating an NPN transistor in an integrated circuit is to form an N+ buried layer in the substrate by selective ion implantation, and to grow an N-type epitaxial layer on top of the buried layer that will serve as the collector of the transistor. An N+ collector sinker may be formed by selectively implanting and diffusing N-type dopant into the epitaxial layer.
The fabrication process is similar for complementary bipolar circuits where both NPN and PNP transistors are used, although extra steps may be needed for the PNP transistor. The extra steps typically include the formation of a P+ buried layer and the P-type collector. To simplify fabrication, a P+ collector sinker may be omitted.
As seen for example in FIG. 1, a conventional fast vertical PNP transistor 10 in a complementary bipolar circuit may contain a P-type vertical conductive region that includes a low resistance buried layer 12 within an N-type region of a substrate 14 that is contacted by a sinker 16 and a collector 18 extending through an N-type epitaxial layer 20.
Typically the breakdown voltage of a fast transistor operating in the GHz frequency range is about 10 volts or less, and the epitaxial layer 20 has a thickness of about 2.5 microns or less. The P-type collector 18 and P+ collector sinker 16 may be formed in epitaxial layers of this thickness with a single implantation and appropriate diffusion. If, however, the breakdown voltage is to be larger, a thicker epitaxial layer will be needed. Epitaxial layers thicker than 2.5 microns may be too thick for a conventional low energy implanter (they do not have enough energy to implant the doping ions to the bottom of the layer), and high energy implanters (e.g., MeV) are needed. High energy implanters are expensive and also have depth limitations. Alternative methods that do not use high energy implanters may compromise transistor high frequency performance. One prior art method that is disclosed in U.S. Pat. No. 5,023,194 issued Jun. 11, 1991 to Gianella suggests simultaneously up and down diffusing collector regions deposited on opposing surfaces of an epitaxial layer to join the two diffused portions into a single vertical collector. The approach suffers from long diffusion time (and associated costs), and does not afford the opportunity to include a buried layer and a sinker adjacent the down-and-up diffused collector.
Accordingly, it is an object of the present invention to provide a novel method of fabricating a vertical conductive region in a semiconductor device that obviates the problems of the prior art.
It is a further object of the present invention to provide a novel method of fabricating high-voltage, vertical PNP transistors, operable in the GHz range, with conventional dopant implants.
It is still a further object of the present invention to provide a novel method of making vertical conductive regions in which plural epitaxial layers are separately implanted with dopant before the next layer is grown to form a unitary component of a vertical transistor.
It is another object of the present invention to provide a novel method of fabricating a vertical conductive region in a vertical PNP transistor in which the manufacturing process does not limit the thickness of the vertical conductive region.
It is still another object of the present invention to provide a novel method of fabricating vertical bipolar PNP transistors in which conventional implants in each of separate epitaxial layers implant dopant into each layer before the next layer is grown to construct vertical transistor sinker and collector regions.